UFS Design Verification Engineer
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Your Main Responsibilities
- Develop and maintain SystemVerilog/UVM-based verification environments, testbenches, and test cases.
- Verify UFS functionality, protocol behavior, and relevant corner cases across supported configurations.
- Execute and validate regressions, investigate failures, and partner with design and integration teams to drive resolution.
- Implement and track code and functional coverage, driving closure against defined verification objectives.
- Maintain clear verification documentation, including test plans, results, and issue tracking.
Requirements
- 7–8 years of relevant ASIC/IP design verification experience.
- Strong understanding of ASIC design verification methodologies and principles.
- Proficiency in SystemVerilog and UVM.
- Strong UFS protocol knowledge.
- Demonstrated experience in testbench and testcase development, regression execution and validation, and code and functional coverage.
- Preferred: proficiency in Perl and/or Python scripting.
- Preferred: experience working with foundry data from TSMC, Intel, and/or Samsung.
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