UAL Design Verification Engineer
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Your Main Responsibilities
- Develop and maintain SystemVerilog/UVM-based verification environments, testbenches, and test cases.
- Verify UAL functionality and interfaces, with particular focus on Ethernet integration and basic PCIe protocol interactions.
- Execute regressions, analyze failures, and collaborate with design and integration teams to resolve issues.
- Develop and track code and functional coverage, driving coverage closure against the verification plan.
- Document verification results, issues, and readiness for project milestones.
Requirements
- 4–5 years of relevant ASIC/IP design verification experience.
- Strong understanding of ASIC design verification methodologies and principles.
- Proficiency in SystemVerilog and UVM.
- Strong UAL and Ethernet knowledge, together with basic PCIe protocol knowledge.
- Demonstrated experience in testbench and testcase development, regression execution and validation, and code and functional coverage.
- Preferred: proficiency in Perl and/or Python scripting.
- Preferred: experience working with foundry data from TSMC, Intel, and/or Samsung.
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